Alphabet’s hardware strategy is no longer well described as an internal effort to make AI computation cheaper. The more consequential development is the gradual formation of a full-stack infrastructure proposition: Google-designed TPUs support its own products and Cloud capacity, are being made available through external hardware-system sales, and are linked to models, networking, software frameworks and distribution. TPUs are Google-designed ASICs and specialised machine-learning accelerators intended for both training and inference. 2,6,44,19,11 The strategic unit is therefore not the processor by itself, but the system in which chip design, Cloud delivery and software adoption reinforce one another. 46,54
This is a substantive strategic pillar rather than a speculative one. Alphabet’s in-house AI-chip development is supported by three independent sources, while related reporting identifies both an existing homegrown-chip capability and a new AI-chip team in Israel. 21,49,50,47,62 At the same time, Alphabet’s position must be understood in its proper industrial setting. It is pursuing custom silicon while remaining a purchaser of Nvidia chips, and Nvidia’s stronger results, guidance and reported Rubin demand are constructive evidence for the wider AI-infrastructure spending environment—not evidence of Alphabet-specific financial performance. 28,55,64
We must therefore distinguish between the short-run question of securing and deploying compute, and the longer-run question of where the economics of that compute will accrue. In the short run, Alphabet’s custom-silicon program is constrained by the same concentrated supply chain that affects its peers. In the longer run, the program may improve its ability to tailor infrastructure, reduce particular forms of supplier dependence and commercialise its own systems. Neither proposition implies that Nvidia GPUs, or the suppliers beneath custom silicon, become dispensable.
A Platform Rather Than a Standalone Chip
Google Cloud has already translated the TPU program into a deployable platform. TPUs are available through Compute Engine, Google Kubernetes Engine and Vertex AI, with supporting quickstarts, guides and operational documentation. 51,52,53 The available lineup includes TPU7x/Ironwood, TPU v6e/Trillium and TPU v5p, while TPU VMs expose the underlying chips and slices group interconnected chips across one or more virtual machines. 9,19 A TPU Pod, in turn, is a contiguous TPU set connected through specialised networking. 8,19
The relevant differentiation is systems integration. Google’s AI Hypercomputer combines optimised hardware, open software, machine-learning frameworks and flexible consumption models, coordinating accelerators and networking as a homogeneous system. 42 Cloud TPU Multislice uses Google’s Jupiter network, while dedicated secondary VPCs in v6e and TPU7x deployments carry high-throughput and cross-slice traffic; GKE-managed DRANET can assign TPU communication drivers. 15 This architecture matters because modern AI deployment is not governed by accelerator throughput alone. Data-parallel training requires frequent high-speed communication, and large deployments require specialised software to coordinate tens or hundreds of thousands of accelerators. 16,63
Ironwood illustrates the direction of technical emphasis. TPU7x is Google’s seventh-generation architecture, with 2,307 TFLOPs of peak BF16 compute per chip and 960 GB of listed memory; a four-chip tpu7x-standard-4t configuration lists 768 GiB of HBM. 12,33,19 More fundamentally, Ironwood employs a systolic array that reuses data as it passes through multiply-accumulate units instead of continually retrieving it from memory. 19,33 The design is an instructive example of an industry-wide adjustment: increasing performance requires not merely more arithmetic capacity, but more efficient treatment of memory movement, bandwidth and interconnect.
That adjustment does not make memory less important. Alphabet’s Ironwood specifications indicate 192 GB of HBM per chip, six times Trillium’s capacity, and the broader evidence shows that HBM is becoming increasingly central to AI systems. 35,1,3,4,5,7,30 Memory capacity and bandwidth are especially material where persistent agents, long-context inference and multi-turn architectures keep more information resident for longer; these workload pressures can outpace efficiency gains from activating only the model components needed for a task. 29,18,27,35
GPUs Remain Part of the Equilibrium
Custom silicon should not be confused with a clean replacement strategy. Google is expanding native PyTorch support and using PyTorch/JAX efforts to reduce CUDA-related porting friction, but many Cloud customers retain CUDA dependence and therefore continue to demand Nvidia GPUs. 31,33 Google consequently offers both GPUs and TPUs, including B200-based A4 VMs and A3 pools containing H100 GPUs. 10,17,15,57
This coexistence reflects different elasticities of substitution across workloads. TPUs may be attractive where workloads fit JAX or PyTorch/XLA and where customers benefit from pod-scale architecture, but a GPU VM and a TPU chip-hour are not directly comparable units of economic value. 20 The practical contest is therefore less a binary ASIC-versus-GPU event than a continuing allocation of workloads between general-purpose and specialised systems. One industry assessment similarly expects ASIC unit shipments potentially to overtake Nvidia GPU shipments while Nvidia retains the larger revenue share. 24
The Supply Chain Is the Binding Constraint
Alphabet’s ownership of processor architecture changes the locus of dependence; it does not remove dependence. Google reportedly reserves upstream HBM capacity directly and, under a described semi-custom model, pools or cross-allocates HBM capacity, TSMC wafer starts and high-density substrate capacity with its partner. 31 This is best understood as an effort to manage a circulatory system of constrained inputs rather than as a simple purchasing arrangement.
The reason is straightforward. HBM supply is concentrated among SK Hynix, Micron and Samsung, while the integration of HBM stacks with logic dies makes substitution more difficult than it is in commodity DRAM. 24 Advanced packaging, customer-design integration, lengthy qualification and switching costs can make those relationships stickier still. 56 At the fabrication layer, TSMC is reported to hold more than 90% of sub-5-nanometre leading-edge capacity and to face demand it cannot fully meet. 61,24
The available evidence already identifies the resulting bottlenecks. Demand for custom TPUs reportedly exceeded TSMC packaging capacity, while a separate report says TPU demand exceeds its manufacturing capacity. 39,22 Expansion at TSMC, ASE Technology and Amkor may alleviate particular stages of the chain, but constraints are reported to be migrating toward HBM, ABF substrates and high-layer-count printed circuit boards. 59 Additional foundry capacity alone, in other words, does not necessarily restore the system to equilibrium.
HBM4 presents the sharper near-term uncertainty. One report calls its availability decisive for TPU ramp plans, while two sources say Nvidia has secured the vast majority of Samsung HBM4 capacity through advance commitments. 31 Google is reportedly evaluating HBM3E as a fallback. 31 Yet scarcity should not be extrapolated indefinitely: yields may improve, capacity additions could ultimately produce a glut, Samsung has announced a major HBM4 expansion, and SK Hynix is investing $12.92 billion in a packaging and testing facility expected to be completed by the end of 2027. 56,36,43,40
The appropriate conclusion is conditional. Early reservations can be valuable while supply is tight, but their value depends on future demand, yields and capacity—not simply on present scarcity.
Commercialisation Has Begun, but Its Scale Is Not Yet Disclosed
Alphabet has moved beyond internal TPU use and Cloud rental. It historically rented TPUs through Google Cloud rather than selling them, but now sells or rents TPU systems and capacity that encompass hardware, software, installation and support. 37,12,38,58,37 Q2 FY2026 was the first period in which Alphabet recognised TPU sales revenue, also described as its first reporting of external hardware sales. 23,41
This is a meaningful change in the strategy’s economic perimeter. Alphabet can potentially capture TPU-system revenue while retaining customers within Cloud services. 37 But present financial evidence does not justify treating that potential as established scale. Direct TPU-system revenue has been described as small so far, and the undisclosed TPU contribution makes its role in overall Cloud growth difficult to determine. 37,11 Forecasts for an approximately $8 billion TPU business in 2026, material revenue in 2027 or a possible 2028 outcome remain forecasts rather than realised results. 32,54,14
There are encouraging but less broadly corroborated signals. Thomas Kurian stated that Google Cloud’s TPU accelerator business is more than twice the next-largest hyperscaler accelerator business and that in-house processors have about half the payback of GPUs. 11 Reports also identify demand exceeding manufacturing capacity. 22 These claims point to a potentially valuable commercial position, but the absence of disclosed pricing, customer-adoption, performance and market-share data makes the current monetisation trajectory inherently difficult to measure. 48,52,53
A Concentrated Partnership Requires Diversification
Broadcom is pivotal to this industrial arrangement. It is named as Google’s custom-silicon partner, is described as Google’s lead vendor in one account, and has agreements concerning Alphabet collaboration and networking components for next-generation AI racks extending as late as 2031. 25,34,11,37 Broadcom’s model—co-designing XPUs or ASICs for a particular customer, model or application—is distinct from Nvidia’s general-purpose GPU model, though the two types of hardware can be complementary. 13
The relationship provides continuity but creates concentration. Google is described as dependent on Broadcom, and Broadcom’s custom-ASIC order book is reported to be anchored by Google with commitments through 2031. 33,60 Google has reportedly secured baseline Broadcom wafer commitments through 2030 and contingent 2-nanometre capacity as a hedge. 31 These measures may improve resilience in the short run; they also demonstrate how much physical capacity has become a strategic asset.
Alphabet is nevertheless attempting to diversify. Reports attribute Broadcom’s omission from initial TPU V9 planning partly to disagreement over semi-custom economics and partly to Broadcom’s heavily committed production pipeline. 31 MediaTek is identified as a secondary supplier, but enterprise customers may prefer validated, high-volume products to unproven MediaTek designs. 13,31 This is the central qualification problem of multisourcing: a second supplier improves bargaining power and resilience only after its design is accepted, qualified and available at volume.
Implication: Infrastructure Leadership Requires Supply Leadership
Alphabet’s AI-hardware strategy is becoming more coherent: proprietary silicon is embedded in a Cloud platform, supported by system-level networking and software, commercialised externally, and retained alongside Nvidia GPUs where customer and workload requirements warrant them. The evidence supports that direction of travel. 26,54,11,33,45
But the industry’s present equilibrium is defined by a countervailing fact. Custom TPUs reduce reliance on merchant accelerators while leaving Alphabet exposed to concentrated dependencies in foundry capacity, HBM, substrates, advanced packaging and supplier qualification. 33,59 The interesting question is not whether Alphabet can design a competitive chip; the material establishes that it is already doing so. It is whether the company can turn design ownership into sustained physical output and commercially adopted systems across successive hardware generations.
Under current conditions, the most useful indicators are therefore neither peak FLOPS nor broad AI-spending narratives alone. They are HBM availability, packaging capacity, the pace at which alternative suppliers qualify, TPU-system revenue disclosure, and the continuing balance between TPU-optimised workloads and GPU demand. Those variables will determine whether Alphabet’s vertical integration becomes a durable infrastructure advantage or remains constrained by the supply chain on which every advanced accelerator ultimately depends.